Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

1.2. Supported Features

The Low Latency 50G Ethernet Intel® FPGA IP core supports the following features:
  • PHY features:
    • Soft PCS logic that interfaces seamlessly to the Stratix® 10 FPGA 25.78125 gigabits per second (Gbps) serial transceivers.
    • Auto-negotiation (AN) as defined in the IEEE Standard 802.3-2015 Clause 73 and 25G & 50G Ethernet Specification, Schedule 3.
    • Link training (LT) as defined in the IEEE Standard 802.3-2015 Clauses 92 and 93 and 25G & 50G Ethernet Specification, Schedule 3.
  • Frame structure control features:
    • Support for jumbo packets, defined as packets greater than 1500 bytes.
    • Receive (RX) CRC removal and pass-through control.
    • Transmit (TX) CRC generation.
    • RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
    • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Frame monitoring and statistics:
    • RX CRC checking and error reporting.
    • Optional RX strict SFD checking per IEEE specification.
    • RX malformed packet checking per IEEE specification.
    • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Debug and testability features:
    • Programmable serial PMA local loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
    • Optional access to Native PHY Debug Master Endpoint (NPDME) for serial link debugging or monitoring PHY signal integrity.
  • User system interfaces:
    • Avalon® memory-mapped management interface to access the IP control and status registers.
    • Avalon® streaming data path interface connects to client logic.
    • Configurable ready latency of 0 or 3 clock cycles for Avalon® streaming TX interface.
    • Hardware and software reset control.