Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

4.8.1. TX Pause/PFC Flow Control Transmission

An XON/XOFF request triggers the IP core to transmit a Pause or PFC flow control frame on the Ethernet link. You can control XON/XOFF requests using the TX flow control registers or the pause_insert_tx0 and pause_insert_tx1 input signals.

You can specify whether the IP core accepts XON/XOFF requests in 1-bit or 2-bit format by updating the TX Flow Control CSR XON/XOFF Request register field. By default, the IP core assumes 1-bit requests.