Low Latency 50G Ethernet Intel FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683675
Date 12/14/2020
Public
Document Table of Contents

4.6.2. Bit Order For TX and RX Datapaths

The TX bit order matches the placement shown in the PCS lanes as illustrated in IEEE Standard for Ethernet, Section 4, Figure 49-5. The RX bit order matches the placement shown in IEEE Standard for Ethernet, Section 4, Figure 49-6.