Visible to Intel only — GUID: iot1605491004550
Ixiasoft
6.6.1. AN/LT Sequencer Config
6.6.2. AN/LT Sequencer Status
6.6.3. Auto Negotiation Config Register 1
6.6.4. Auto Negotiation Config Register 2
6.6.5. Auto Negotiation Status Register
6.6.6. Auto Negotiation Config Register 3
6.6.7. Auto Negotiation Config Register 4
6.6.8. Auto Negotiation Config Register 5
6.6.9. Auto Negotiation Config Register 6
6.6.10. Auto Negotiation Status Register 1
6.6.11. Auto Negotiation Status Register 2
6.6.12. Auto Negotiation Status Register 3
6.6.13. Auto Negotiation Status Register 4
6.6.14. Auto Negotiation Status Register 5
6.6.15. Link Training Config Register 1
6.6.16. Link Training Config Register 2
6.6.17. Link Training Status Register 1
6.6.18. Link Training Config Register for Lane 0
6.6.19. Link Training Frame Contents for Lane 0
6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0
6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0
6.6.22. Local Link Training Parameters
6.6.23. Link Training Config Register for Lane 1
6.6.24. Link Training Frame Contents for Lane 1
6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1
6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1
6.6.27. Link Training Config Register for Lane 2
6.6.28. Link Training Frame Contents for Lane 2
6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2
6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2
6.6.31. Link Training Config Register for Lane 3
6.6.32. Link Training Frame Contents for Lane 3
6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3
6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
Visible to Intel only — GUID: iot1605491004550
Ixiasoft
4.6.2. Bit Order For TX and RX Datapaths
The TX bit order matches the placement shown in the PCS lanes as illustrated in IEEE Standard for Ethernet, Section 4, Figure 49-5. The RX bit order matches the placement shown in IEEE Standard for Ethernet, Section 4, Figure 49-6.
Related Information