Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

6.6.11. Auto Negotiation Status Register 2

This register provides the upper bits of the AN RX Base page received from the link partner.

Offset: 0xC8

Access: RO

Auto Negotiation Status Register 2 Fields

Bit Name Description Access Reset
31:0 lp_base_page_high Link Partner Base Page (upper bits)

[29:5]: Link partner Technology Ability bits

[4:0]: TX Nonce bits

RO 0x0