Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Document Table of Contents

1.5.1. Simulation Environment

Intel® performs the following tests on the Low Latency 50G Ethernet core in the simulation environment using internal and third-party standard bus functional models (BFM):

  • Constrained random tests that cover randomized frame size and contents.
  • Assertion based tests to confirm proper behavior of the IP core with respect to the specification.
  • Extensive coverage of our runtime configuration space and proper behavior in all possible modes of operation.