Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

3. IP Core Parameters

The Low Latency 50G Ethernet IP parameter editor provides the parameters you can set to configure the Low Latency 50G Ethernet IP core and simulation testbenches.

The Low Latency 50G Ethernet parameter editor includes an Example Design tab. For more information, refer to the Low Latency 50G Ethernet Intel® FPGA IP Core Design Example User Guide.

Table 9.  IP Core Parameters
Parameter Range Default Setting Description
Main: General Options
Ready Latency 0

3

 0

Selects the Ready Latency value on the TX client interface. Ready Latency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l1_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon® Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the datapath.

If you set the Ready Latency to 3 and turn on standard flow control, data might be delayed in the IP core while the IP core is backpressured.

Main: PCS/PMA Options
PHY reference frequency 644.53125 MHz

322.265625 MHz

 644.53125 MHz Reference clock frequency for PHY.
Main: MAC Options
Enable TX CRC insertion Enabled

Disabled

 Enabled When enabled, the TX MAC calculates and insert a CRC at the end of the frame.
Enable link fault generation Enabled

Disabled

 Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Standard for Ethernet. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled

Disabled

 Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled

Disabled

 Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic. These statistics counters can be read via the Avalon memory-mapped bus.
Enable Strict SFD Check Enabled

Disabled

 Disabled When enabled, the IP core can implement strict SFD checking in RX MAC, depending on register settings.
Main: Flow Control Options
Enable MAC flow control Enabled

Disabled

 Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames. Register settings control flow control behavior, including whether the IP core implements standard flow control or priority-based flow control.

If you turn on standard flow control and set the Ready Latency to 3, data might be delayed in the IP core while the IP core is backpressured.

Number of queues 1 to 8 1 Specifies the number of queues used in managing flow control.
Main: Debug Options
Enable Native PHY Debug Master Endpoint (NPDME) Enabled

Disabled

 Disabled When on, an embedded Native PHY Debug Master Endpoint connects internally to the Avalon-MM slave interface for the dynamic reconfiguration. The Native PHY Debug Master Endpoint can access the reconfiguration space of the transceiver. It can perform certain tests and debug functions via JTAG using System Console.
Enable JTAG to Avalon Master Bridge Enabled

Disabled

 Disabled When selected, IP includes a JTAG to Avalon-MM Master bridge connecting internally to status and reconfig registers. This allows the Ethernet Link Inspector to be run using System Console.
AN/LT: Basic Options
Enable AN/LT Enabled

Disabled

 Disabled

If this parameter is turned on, the IP core supports auto negotiation as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G Ethernet Consortium Schedule 3, and link training as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G Ethernet Consortium Schedule 3.

If this parameter is turned off, the IP core does not support these features, and the other parameters on this tab are not available.

Status clock rate 100 to 162 MHz 100 MHz Sets the expected incoming i_reconfig_clk frequency. The input clock frequency must match the frequency you specify for this parameter.

The IP core is configured with this information to ensure the IP core measures the link fail inhibit time accurately (determines the value of the Link Fail Inhibit timer (IEEE 802.3 clause 73.10.2) correctly).

AN/LT: Auto-Negotiation
Enable Auto-Negotiation Enabled

Disabled

 Enabled

If this parameter is turned on, the IP core includes logic to implement auto negotiation as defined in Clause 73 of IEEE Std 802.3–2015. If this parameter is turned off, the IP core does not include auto negotiation logic and cannot perform auto negotiation.

Link fail inhibit time 500 to 510 ms 504 ms Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto Negotiation for Backplane Ethernet in IEEE Standard 802.3–2015.

The IP core asserts the o_rx_pcs_ready signal to indicate link status is OK.

Enable CR Technology Ability Enabled

Disabled

 Enabled If this parameter is turned on, the IP core advertises CR capability by default. If this parameter is turned off, but auto negotiation is turned on, the IP core advertises KR capability by default.
Auto-Negotiation Master Lane 0

Lane 1

Lane 2

Lane 3

 Lane 0 Selects the master channel for auto negotiation.

The IP core does not provide a mechanism to change the master channel dynamically. The value you set in the parameter editor cannot be changed during operation.

Pause Ability–C0 Enabled

Disabled

 Enabled If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.
Pause Ability–C1 Enabled

Disabled

 Enabled If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.
AN/LT: Link Training
Enable Link Training Enabled

Disabled

 Enabled

If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 92 of IEEE Std 802.3–2015.

Number of frames to send at end of training 127

255

 127

Specifies the number of additional training frames the local link partner delivers after training is complete to ensure that the link partner can correctly detect the local receiver state.

Enable Clause 72 PRBS11 generation Enabled

Disabled

 Disabled If turned on, the IP core includes logic to generate the legacy Clause 72 PRBS pattern, in addition to the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015. If turned off, the IP core generates only the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015.
AN/LT: Link Training PMA Parameters
VMAXRULE 0 to 31 30 Specifies the maximum VOD. The default value, 30, represents 1200 mV. This default value is the maximum value the device should drive.
VMINRULE 0 to 31 6 Specifies the minimum VOD. The default value, 6, represents 165 mV. This default value is the minimum value the device should drive.
VODMINRULE 0 to 31 14 Specifies the minimum VOD for the first tap.

The default value, 14, represents 440 mV.

VPOSTRULE 0 to 25 25 Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting.
VPRERULE 0 to 16 16 Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting.
PREMAINVAL 0 to 31 30 Specifies the Preset VOD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3–2015.
PREPOSTVAL 0 to 25 0 Specifies the preset Post-tap value.
PREPREVAL 0 to 16 0 Specifies the preset Pre-tap value.
INITMAINVAL 0 to 31 25 Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3–2015.
INITPOSTVAL 0 to 25 13 Specifies the initial Post-tap value.
INITPREVAL 0 to 16 3 Specifies the initial Pre-tap value.
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