Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Public

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7.1.3.1. Viewing Architecture-Specific Design Information in Chip Planner

The Chip Planner allows you to view architecture-specific information related to your design. By enabling the options in the Layers Settings pane and Properties tab, you can view:
  • Device routing resources used by your design—view how blocks are connected, as well as the signal routing that connects the blocks.
  • LE configuration—view logic element (LE) configuration in your design. For example, you can view which LE inputs are used; whether the LE utilizes the register, the look-up table (LUT), or both; as well as the signal flow through the LE.
  • ALM configuration—view ALM configuration in your design. For example, you can view which ALM inputs are used; whether the ALM utilizes the registers, the upper LUT, the lower LUT, or all of them. You can also view the signal flow through the ALM.
  • I/O configuration—view device I/O resource usage. For example, you can view which components of the I/O resources are used, whether the delay chain settings are enabled, which I/O standards are set, and the signal flow through the I/O.
  • PLL configuration—View phase-locked loop (PLL) configuration in your design. For example, you can view which control signals of the PLL are used with the settings for your PLL.
  • Timing—view the delay between the inputs and outputs of FPGA elements. For example, you can analyze the timing of the DATAB input to the COMBOUT output.