Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Public

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4.1.2. Physical Synthesis Options

The Intel® Quartus® Prime software provides physical synthesis optimization options to improve fitting results. To access these options, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
Note: To disable global physical synthesis optimizations for specific elements of your design, assign the Netlist Optimizations logic option to Never Allow to the specific nodes or entities.
Table 9.  Physical Synthesis Options
Option Description
Advanced Physical Synthesis Uses the physical synthesis engine to perform combinational and sequential optimization during fitting to improve circuit performance.
Netlist Optimizations You can use the Assignment Editor to apply the Netlist Optimizations logic option. Use this option to disable physical synthesis optimizations for parts of your design. This option is available only for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Allow Register Duplication

Allows the Compiler to duplicate registers to improve design performance. When you enable this option, the Compiler copies registers and moves some fan-out to this new node. This optimization improves routability and can reduce the total routing wire in nets with many fan-outs.

If you disable this option, this disables optimizations that retime registers. This setting affects Analysis & Synthesis and the Fitter. This option is available only for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Allow Register Merging

Allows the Compiler to remove registers that are identical to other registers in the design. When you enable this option, in cases where two registers generate the same logic, the Compiler deletes one register, and the remaining registers fan-out to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing intentional use of duplicate registers.

If you disable register merging, the Compiler disables optimizations that retime registers.

This setting affects Analysis & Synthesis and the Fitter.