Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Public

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6.5.8.13.6. Register RAMS and DSPs

If your design includes long timing paths going to and from RAMs and DSPs, you must fully register the RAMs and DSPs.

RAM and DSP performance can vary, depending on the memory mode. A memory using read-during-write mode is slower than a memory that uses a different mode. Refer to your FPGA device documentation for hardware performance specifications. If the fMAX is restricted due to mode, change to a different memory mode with a higher performance specification, if possible.