Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
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5.2.3.10. Guideline: Retarget or Balance DSP Blocks

A design might not fit because it requires more DSP blocks than the target FPGA device has available.

You can implement all DSP block functions with logic cells, so you can retarget some of the DSP blocks to logic to obtain a fit.

If the DSP function was created with the parameter editor, open the parameter editor and edit the function so it targets logic cells instead of DSP blocks. The Intel® Quartus® Prime software uses the DEDICATED_MULTIPLIER_CIRCUITRY IP core parameter to control the implementation.

DSP blocks also can be inferred from your HDL code for multipliers, multiply-adders, and multiply-accumulators. You can turn off this inference in your synthesis tool. When you are using Intel® Quartus® Prime synthesis, you can disable inference by turning off the Auto DSP Block Replacement logic option for your entire project. Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis). Turn off Auto DSP Block Replacement. Alternatively, you can disable the option for a specific block with the Assignment Editor.

The Intel® Quartus® Prime software also offers the DSP Block Balancing logic option, which implements DSP block elements in logic cells or in different DSP block modes. The default Auto setting allows DSP block balancing to convert the DSP block slices automatically as appropriate to minimize the area and maximize the speed of the design. You can use other settings for a specific node or entity, or on a project-wide basis, to control how the Intel® Quartus® Prime software converts DSP functions into logic cells and DSP blocks. Using any value other than Auto or Off overrides the DEDICATED_MULTIPLIER_CIRCUITRY parameter used in IP core variations.

For designs with large number of low-precision arithmetic operations, such as additions and multiplications, you can enable fractal synthesis optimizations. Fractal synthesis optimizations are useful for high-throughput, arithmetic-intensive designs that exceed all available DSP resources. These optimizations are beneficial in designs with large numbers of low-precision arithmetic operations, such as additions and multiplications.