Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Document Table of Contents

8. Using the ECO Compilation Flow

In a typical FPGA project development cycle, the specification of the programmable logic portion of the design can change during the design process. The Intel® Quartus® Prime software supports these last-minute, targeted engineering change orders (ECOs), even after full compilation is complete.

ECOs typically occur during the design verification stage. For example, during verification you may determine that the design requires a small change, such as a netlist connection change, correcting a LUT logic error, or placing a node in a new location. Implementing an ECO change, rather than changing RTL and fully recompiling the design, requires significantly less time, and changes only the affected logic.

You specify the ECO commands in a Tcl script using the ::quartus::eco package.

Note: The Intel® Quartus® Prime Pro Edition software supports ECOs for Intel® Stratix® 10 and Intel® Agilex™ devices only.

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