Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Document Table of Contents

3.6.2. Schematic Symbols

The symbols for nodes in the schematic represent elements of your design netlist. These elements include input and output ports, registers, logic gates, Intel primitives, high-level operators, and hierarchical instances.
Note: The logic gates and operator primitives appear only in the RTL Viewer. Logic in the Technology Map Viewer is represented by atom primitives, such as registers and LCELLs.
Table 6.  Symbols in the Schematic View This table lists and describes the primitives and basic symbols that you can display in the schematic view of the RTL Viewer and Technology Map Viewer.
Symbol Description

Wire indicator and net ripper

Indicates the net signal flow direction into or out of the pin or port. There can be symbols in both directions due to automatic net bundling from the connectivity. You can click the net to highlight the signal flow details in the schematic.
I/O Ports

An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top‑level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths.

Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right‑most side of the schematic.

I/O Connectors

An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click the connector to jump to the appropriate page.
OR, AND, XOR Gates

An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted.

A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer with more than two inputs is displayed as an operator.

A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port.

A latch/DFF (data flipflop) primitive. A DFF has the same ports as a latch and a clock trigger. The other flipflop primitives are similar:
  • DFFEA (data flipflop with enable and asynchronous load) primitive with additional ALOAD asynchronous load and ADATA data signals
  • DFFEAS (data flipflop with enable and synchronous and asynchronous load), which has ASDATA as the secondary data port
Atom Primitive

An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details.
Other Primitive

Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name.

An instance in the design that does not correspond to a primitive or operator (a user‑defined hierarchy block). The symbol displays the port name and the instance name.
Encrypted Instance

A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted.

A synchronous memory instance with registered inputs and optionally registered outputs. The symbol shows the device family and the type of memory block. This figure shows a true dual-port memory block in a Stratix M-RAM block.

A constant signal value that is highlighted in gray and displayed in hexadecimal format by default throughout the schematic.
Table 7.  Operator Symbols in the RTL Viewer Schematic View     The following lists and describes the additional higher level operator symbols in the RTL Viewer schematic view.
Symbol Description

An adder operator:

OUT = A + B

A multiplier operator:

OUT = A ¥ B

A divider operator:

OUT = A / B


A left shift operator:

OUT = (A << COUNT)

A right shift operator:

OUT = (A >> COUNT)

A modulo operator:

OUT = (A%B)

A less than comparator:

OUT = (A<:B:A>B)

A multiplexer:


The data range size is 2sel range size

A selector:

A multiplexer with one-hot select input and more than two input signals

A binary number decoder:

OUT = (binary_number (IN) == x)

for x = 0 to

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