Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Public
Document Table of Contents

6.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box

The Periphery to Core Placement and Routing Optimization setting specifies whether the Fitter optimizes targeted placement and routing on direct connections between periphery logic and registers in the FPGA core.

You can optionally perform periphery to core optimizations by instance with settings in the Assignment Editor.

  1. In the Intel® Quartus® Prime software, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
  2. In the Advanced Fitter Settings dialog box, for the Periphery to Core Placement and Routing Optimization option, select one of the following options depending on how you want to direct periphery to core optimizations in your design:
    1. Select Auto to direct the software to automatically identify transfers with tight timing windows, place the core registers, and route all connections to or from the periphery.
    2. Select On to direct the software to globally optimize all transfers between the periphery and core registers, regardless of timing requirements.
      Note: Setting this option to On in the Advanced Fitter Settings is not recommended. The intended use for this setting is in the Assignment Editor to force optimization for a targeted set of nodes or instance.
    3. Select Off to disable periphery to core path optimization in your design.

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