Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 9/26/2022
Public

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6.5.8.8.1. Manual Register Duplication

Synthesis tools support options or attributes that specify the maximum fan-out of a register. When using Intel® Quartus® Prime synthesis, you can set the Maximum Fan-Out logic option in the Assignment Editor to control the number of destinations for a node so that the fan-out count does not exceed a specified value. You can also use the maxfan attribute in your HDL code. The software duplicates the node as required to achieve the specified maximum fan-out.

Logic duplication using Maximum Fan-Out assignments normally increases resource utilization, and can potentially increase compilation time, depending on the placement and the total resource usage within the selected device.

The improvement in timing performance that results from Maximum Fan-Out assignments is design-specific. This is because when you use the Maximum Fan-Out assignment, the Fitter duplicates the source logic to limit the fan-out, but does not control the destinations that each of the duplicated sources drive. Therefore, it is possible for duplicated source logic to be driving logic located all around the device. To avoid this situation, you can use the Manual Logic Duplication logic option.

If you are using Maximum Fan-Out assignments, benchmark your design with and without these assignments to evaluate whether they give the expected improvement in timing performance. Use the assignments only when you get improved results.

You can manually duplicate registers in the Intel® Quartus® Prime software regardless of the synthesis tool used. To duplicate a register, apply the Manual Logic Duplication logic option to the register with the Assignment Editor.

Note: Some Fitter optimizations may cause a small violation to the Maximum Fan-Out assignments to improve timing.