7.2. Defining Logic Lock Placement Constraints
A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region. When you constrain design nodes to a Logic Lock region, the Fitter always places those nodes within the region resulting in more predictable results with each design iteration.
Your floorplan can contain multiple Logic Lock regions, depending on your design characteristics. You can also define a routing region as part of a Logic Lock region. The routing region specifies the routing area constraint.
The Chip Planner makes it easy to visualize and constrain device resources within a device floorplan. You can draw or specify the dimensions of a Logic Lock region in the floorplan using the Logic Lock Regions window. After running synthesis or fitting, you can then assign design nodes as members of the region to implement the constraint.
To detect and resolve any potential problems with Logic Lock regions in your project, click Report DRC to run the Design Assistant to check for the FLP rule category. FLP Design Assistant rules detect possible issues with floorplanning and Logic Lock regions.
The Logic Lock Regions Window
Defining Logic Lock Regions
Customizing the Shape of Logic Lock Regions
Assigning Device Pins to Logic Lock Regions
Viewing Connections Between Logic Lock Regions in Chip Planner
Example: Placement Best Practices for Intel Arria 10 FPGAs
Migrating Assignments between Intel Quartus Prime Standard Edition and Intel Quartus Prime Pro Edition
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