3.3. RTL Viewer Overview
You can view results after Analysis and Elaboration for designs that use any supported Intel® Quartus® Prime design entry method, including Verilog HDL Design Files (.v), SystemVerilog Design Files (.sv), VHDL Design Files (.vhd), AHDL Text Design Files (.tdf), or schematic Block Design Files (.bdf).
You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) for designs that generate Verilog Quartus Mapping File (.vqm) or Electronic Design Interchange Format (.edf) files through a synthesis tool.
- For designs synthesized with the Intel® Quartus® Prime Pro Edition synthesis, this view shows how the Intel® Quartus® Prime software interprets the design files.
- For designs synthesized with a third-party synthesis tool, this view shows the netlist that the synthesis tool generates.
To run the RTL Viewer for an Intel® Quartus® Prime project, first analyze the design to generate an RTL netlist. To analyze the design and generate an RTL netlist, click Processing > Start > Start Analysis & Elaboration. You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Intel® Quartus® Prime compilation flow.
To open the RTL Viewer, click Tools > Netlist Viewers > RTL Viewer.
Maximizing Readability in RTL Viewer
Running the RTL Viewer
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