7.3. Defining Virtual Pins
By making assignments to virtual pins, you can ensure that the Fitter places those pins in the same device region as the corresponding internal nodes in the top-level module. You can apply the Virtual Pin option to successfully compile a Logic Lock module that has more pins than the target device. The Virtual Pin option can enable timing analysis of a design module that more closely matches the performance of the module after you integrate it into the top-level design.
You can create and assign virtual pins to an I/O element using the Virtual Pin logic option in the Assignment Editor (Assignments > Assignment Editor).
When you apply the Virtual Pin assignment to an input pin, the pin no longer appears as an FPGA pin. Rather, the Compiler fixes the virtual pin to GND in the design. The virtual pin is not a floating node.
Use virtual pins only for I/O elements in lower-level design entities that become nodes after you import the entity to the top-level design; for example, when compiling a partial design. In the top-level design, you connect these virtual pins to an internal node of another module
To display all assigned virtual pins in the design with the Node Finder, you can set Filter Type to Pins: Virtual. To access the Node Finder from the Assignment Editor, double-click the To field; when the arrow appears on the right side of the field, click and select Node Finder.
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