4.2. Applying Netlist Optimizations
You may have to experiment with available options to see which combination of settings works best for a particular design. Refer to the messages in the compilation report to see the magnitude of improvement with each option, and to help you decide whether you should turn on a given option or specific effort level.
Turning on more netlist optimization options can result in more changes to the node names in the design; bear this in mind if you are using a verification flow, such as the Signal Tap Logic Analyzer or formal verification that requires fixed or known node names.
To find the best results, you can use the Intel® Quartus® Prime Design Space Explorer II (DSE) to apply various sets of netlist optimization options.
WYSIWYG Primitive Resynthesis
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