Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Using Tightly Coupled Memory Effectively

A system can use TCM to achieve maximum performance for accessing a specific code or data section. For example, interrupt-intensive applications can place exception handler code into a TCM to minimize interrupt latency. Similarly, compute-intensive digital signal processing (DSP) applications can place data buffers into TCM for the fastest possible data access.

You can implement one or more of the following functions or modules using TCMs to enhance the performance of your system:

  • Constant access time with no arbitration delays.
  • Separate exception stack for use only while handling interrupts.
  • Fast data buffers
  • Fast sections of code:
    • Fast interrupt handler
    • Critical loop

If the application’s memory requirements are small enough to fit entirely on-chip, it is possible to use tightly coupled memory exclusively for code and data. Larger applications must selectively choose what to include in tightly coupled memory to maximize the cost-performance trade-off.

Consider the following design when using TCMs:

  • Strike a balance between the speed enhancement from caches with the higher speed enhancement from TCMs.
  • Divide the on-chip memory resources equitably for the best combination of TCMs and cache.
  • Locating any information (code or data) within TCMs eliminates cache overhead such as cache flushing, loading, or invalidating.
Note: You can connect Nios® V processor data manager to instruction TCM subordinate port. Like Nios® II processor, the Instruction TCM can map into the processor's data region for memory debugging.