Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

4.3.12. Error Correction Code (ECC)

The Nios® V/g processor core has the option to enable error detection and ECC status for the following internal RAM blocks:

  • Register file
  • Instruction cache
  • Data cache
  • Tightly coupled memories
Each RAM block has its source ID. When an ECC event occurs, the processor transmits the source ID and ECC status to the ECC interface.
  • If the ECC event is a correctable error, the processor continues to operate without correcting the error.
  • If the ECC event is an un-correctable error, the processor halts its current progress and stall. You need to reset either the processor core alone, or entire system
Note: To reset the processor core alone, you need to apply the Reset Request Interface to safely reset the Nios® V processor (Cleared of any outstanding operations). To reset the entire system, you can use the hard reset interface instead.
The ECC interface allows external logic to monitor ECC errors in the Nios® V/g processor. The interface is a conduit and made up of two output signals.
  • cpu_ecc_status: Indicates the error status.
  • cpu_ecc_source: Indicates the error source
Table 86.   cpu_ecc_status
2-bits Encoding ECC Status Effects on Software Next Action
2’b00 No ECC event None None
2’b01 Reserved Not Applicable Not Applicable
2’b10 Correctable single bit ECC error None None
2’b11 Un-correctable ECC error Likely fatal and halts processor Reset either processor or entire system
Table 87.   cpu_ecc_source
4-bits Encoding ECC Source Available
4’b0000 No ECC event Always
4’b0001 General Purpose Register (GPR) Always
4’b0010 Instruction Cache Data RAM Always
4’b0011 Instruction Cache Tag RAM Always
4’b0100 Data Cache Data RAM Always
4’b0101 Data Cache Tag RAM Always
4’b0110 Instruction TCM1 When Instruction TCM1 is present
4’b0111 Instruction TCM2 When Instruction TCM2 is present
4’b1000 Data TCM1 When Data TCM1 is present
4’b1001 Data TCM2 When Data TCM2 is present
4’b1010 Floating Point Register (FPR) When FPU is present
4’b1111 Reserved Not Applicable
Note: Due to a limitation with embedded memory blocks, the simulation model of Nios® V processor does not support ECC on Arria® 10 devices.