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Ixiasoft
4.3.1. General-Purpose Register File
4.3.2. Arithmetic Logic Unit
4.3.3. Multipy and Divide Units
4.3.4. Floating-Point Unit
4.3.5. Custom Instruction
4.3.6. Reset and Debug Signals
4.3.7. Control and Status Registers
4.3.8. Exception Controller
4.3.9. Interrupt Controller
4.3.10. Memory and I/O Organization
4.3.11. RISC-V based Debug Module
4.3.12. Error Correction Code (ECC)
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Ixiasoft
2.3.4.1.1. Instruction Manager Port
Nios® V/c processor instruction bus is implemented as a 32-bit AMBA* 4 AXI-Lite manager port.
The instruction manager port:
- Performs a single function: it fetches instructions to be executed by the processor.
- Does not perform any write operations.
- Can issue successive read requests before data return from prior requests.
- Can prefetch sequential instructions.
- Always retrieves 32-bit of data. Every instruction fetch returns a full instruction word, regardless of the width of the target memory. The widths of memory in the Nios® V/c processor system is not applicable to the programs. Instruction address is always aligned to a 32-bit word boundary.
Interface | Signal | Role | Width | Direction |
---|---|---|---|---|
Write Address Channel | awaddr | Unused | [31:0] | Output |
awprot | Unused | [2:0] | Output | |
awvalid | Unused | 1 | Output | |
awready | Unused | 1 | Input | |
Write Data Channel | wdata | Unused | [31:0] | Output |
wstrb | Unused | [3:0] | Output | |
wvalid | Unused | 1 | Output | |
wready | Unused | 1 | Input | |
Write Response Channel | bresp | Unused | [1:0] | Input |
bvalid | Unused | 1 | Input | |
bready | Unused | 1 | Output | |
Read Address Channel | araddr | Instruction Address (Program Counter) |
[31:0] | Output |
arprot | Unused | [2:0] | Output | |
arvalid | Instruction address valid | 1 | Output | |
arready | Instruction address ready (from memory) |
1 | Input | |
Read Data Channel | rdata | Instruction | [31:0] | Input |
rresp | Instruction response: Non-zero value denotes instruction access fault exception | [1:0] | Input | |
rvalid | Instruction valid | 1 | Input | |
rready | Constant 1 | 1 | Output |