Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

3.3. Processor Architecture

The Nios® V/m processor architecture describes an instruction-set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions.
The Nios® V/m processor architecture defines the following functional units:
  • General-purpose register file
  • Arithmetic logic unit (ALU)
  • Control and status registers (CSR)
  • Exception controller
  • Interrupt controller
  • Instruction bus
  • Data bus
  • RISC-V based debug module
  • ECC module
Figure 4.  Nios® V/m Processor Core Block Diagram