Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Using Cache Memory Effectively

The effectiveness of cache memory to improve performance is based on the following conditions:
  • Regular memory is located off-chip and has a longer access time than on-chip memory.
  • The largest, performance-critical instruction loop is smaller than the instruction cache.
  • The largest block of performance-critical data is smaller than the data cache.

The optimal cache configuration is application-specific, but you can define a configuration that works for a variety of applications. Refer to the following examples:

  • If a Nios® V/g processor system only has fast on-chip memory and never accesses slow off-chip memory, an instruction or data cache is unlikely to boost the performance.
  • If a program's critical loop is 2 KB but the instruction cache is 1 KB, an instruction cache does not improve execution speed. In this case, an instruction cache can actually degrade performance.

Mixing cached and uncached accesses to the same cache line can result in invalid data reads. For example, the following sequences of events causes cache incoherency.

  1. Nios® V processor writes data to cache, creating a dirty data cache line.
  2. Nios® V processor reads data from the same address, but bypassed the cache.

If it is necessary to mix cached and uncached data accesses, flush the corresponding line of data cache after completing the cached accesses and before performing the uncached accesses.