Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

3.1.2. Non-pipelined

Table 18.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Quartus® Prime Software
Quartus® Prime Edition FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Quartus® Prime Pro Edition Cyclone® 10 301 706 0.227 0.170
Arria® 10 332 709
Stratix® 10 348 740
Agilex™ 7 436 703
Agilex™ 5 384 707
Quartus® Prime Standard Edition Cyclone® IV E 117 1598 LE 0.268 0.201
Cyclone® V 144 705 ALM
Arria® V 159 708 ALM
Arria® V GZ 281 658 ALM
Stratix® V 330 641 ALM
Cyclone® 10 LP 135 1604 LE
Arria® 10 316 559 ALM
MAX® 10 127 1619 LE
Table 19.  Benchmark Parameters for Quartus® Prime Software
Parameter Settings/Description
Quartus® Prime Pro Edition Quartus® Prime Standard Edition
Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Quartus® Prime Pro Edition software version 24.1. Maximum performance result are based on 10 seed sweep from Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core (without debug module and internal timer).
  • 128 KB on-chip memory for the instruction and data bus.
  • Interval Timer Core
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 13.2.0
  • CMake Version: 3.27.7
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32i -mabi=ilp32
Intel uses the same Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • Superior Performance with Maximum Placement Effort in Quartus® Prime Pro Edition software.
  • High Performance Effort in Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.