Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Bypassing Cache (Peripheral Region)

The Nios® V/g architecture has two peripheral regions for bypassing the caches. Nios® V/g cores optionally support the peripheral region mechanism to indicate cacheability. In the Platform Designer, the peripheral region cache-ability mechanism allows you to specify a region of address space that is non-cacheable. The peripheral region is any integer power of 2 bytes, from a minimum of 64 kilobytes up to a maximum of 2 gigabytes, and must be located at a base address aligned to the size of the peripheral region. The peripheral region is available provided that an MMU is not present.
Note: Any accesses to the Nios® V processor's debug module or timer module are non-cacheable.
Note: You must place the peripherals driven by the Nios® V/g processor within a defined peripheral region to achieve cache bypass, which is required by a standard design implementation.