Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

3.1.1. Pipelined

Table 16.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Quartus® Prime Software
Quartus® Prime Edition FPGA Used fMAX (MHz) Logic Size Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Quartus® Prime Pro Edition Cyclone® 10 277 1018 ALM 0.63 0.489
Arria® 10 291 1015 ALM
Stratix® 10 327 1207 ALM
Agilex™ 7 410 1193 ALM
Agilex™ 5 347 1232 ALM
Quartus® Prime Standard Edition Cyclone® IV E 107 2831 LE 0.650 0.441
Cyclone® V 145 1253 ALM
Arria® V 146 1222 ALM
Arria® V GZ 264 1215 ALM
Stratix® V 304 1199 ALM
Cyclone® 10 LP 135 2848 LE
Arria® 10 290 1132 ALM
MAX® 10 123 2864 LE
Table 17.  Benchmark Parameters for Quartus® Prime Software
Parameter Settings/Description
Quartus® Prime Pro Edition Quartus® Prime Standard Edition
Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Quartus® Prime Pro Edition software version 24.1. Maximum performance result are based on 10 seed sweep from Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core (without debug module and internal timer).
  • Nios® V/m processor core (without debug module).
  • 128 KB on-chip memory for the instruction and data bus.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 13.2.0
  • CMake Version: 3.27.7
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32i -mabi=ilp32
Intel uses the same Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. The compiler settings are:
  • Superior Performance with Maximum Placement Effort in Quartus® Prime Pro Edition software.
  • High Performance Effort in Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.