Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Instruction Cache

The instruction cache memory has the following characteristics:

  • Direct-mapped cache implementation
  • 32 bytes (8 words) per cache line
  • Configurable size of 1, 2, 4, 8, and 16 KBytes
  • The instruction manager port reads an entire cache line at a time from memory, and issues one read per clock cycle.
  • Critical word first

The instruction byte address size is 32-bit. The size of the tag and index field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-byte line). The instruction fetch fence (fence.i) instruction flushes and invalidates all instruction cache lines.