Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

2.1. Processor Performance Benchmarks

Table 2.   Nios® V/c Processor Performance Benchmarks in Intel FPGA Devices for Quartus® Prime Software
Quartus® Prime Edition FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Quartus® Prime Pro Edition Cyclone® 10 311 406 ALM 0.227 0.17
Arria® 10 331 406 ALM
Stratix® 10 365 425 ALM
Agilex™ 7 427 406 ALM
Agilex™ 5 371 409 ALM
Quartus® Prime Standard Edition Cyclone® IV E 118 1022 LE 0.268 0.201
Cyclone® V 155 423 ALM
Arria® V 175 414 ALM
Arria® V GZ 289 372 ALM
Stratix® V 332 372 ALM
Cyclone® 10 LP 137 1025 LE
Arria® 10 325 355 ALM
MAX® 10 137 1022 LE
Table 3.  Benchmark Parameters for Quartus® Prime Software
Parameter Settings/Description
Quartus® Prime Pro Edition Quartus® Prime Standard Edition
Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Quartus® Prime Pro Edition software version 24.1. Maximum performance result are based on 10 seed sweep from Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/c processor core (without debug module and internal timer).
  • 128 KB on-chip memory for the instruction and data bus.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 13.2.0
  • CMake Version: 3.27.7
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32i -mabi=ilp32

Altera® uses the same Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. The compiler settings are:

  • Superior Performance with Maximum Placement Effort in Quartus® Prime Pro Edition software.
  • High Performance Effort in Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design can change the performance and LE usage. All results are generated from design built with Platform Designer.