Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Instruction Manager Port

Nios® V/g processor instruction bus is implemented as a 32-bit AMBA* 4 AXI manager port.

The instruction manager port:
  • Performs a single function: it fetches instructions to be executed by the processor.
  • Does not perform any write operations.
  • Can issue successive read requests before data return from prior requests.
  • Can prefetch sequential instructions.
  • Always retrieves 32-bit of data. Every instruction fetch returns a full instruction word, regardless of the width of the target memory. The widths of memory in the Nios® V/g processor system is not applicable to the programs. Instruction address is always aligned to a 32-bit word boundary.
Table 70.  Instruction Interface Signals
Interface Signal Role Width Direction
Write Address Channel awaddr Unused [31:0] Output
awlen Unused [7:0] Output
awsize Unused [2:0] Output
awburst Unused [1:0] Output
awprot Unused [2:0] Output
awvalid Unused 1 Output
awready Unused 1 Input
Write Data Channel wdata Unused [31:0] Output
wstrb Unused [3:0] Output
wlast Unused 1 Output
wvalid Unused 1 Output
wready Unused 1 Input
Write Response Channel bresp Unused [1:0] Input
bvalid Unused 1 Input
bready Unused 1 Output
Read Address Channel araddr

Instruction Address

(Program Counter)

[31:0] Output

Read burst length

• 0 for peripheral region access

• 7 for cacheable region access

[7:0] Output
arsize Constant 2 (4 bytes) [2:0] Output
arburst Constant 2 (WRAP) [1:0] Output
arprot Unused [2:0] Output
arvalid Instruction address valid 1 Output

Instruction address ready

(from memory)

1 Input
Read Data Channel rdata Instruction [31:0] Input
rresp Instruction response: Non-zero value denotes instruction access fault exception [1:0] Input
rlast Last transfer in a read burst 1 Input
rvalid Instruction valid 1 Input
rready Constant 1 1 Output