Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

3.3.9. Error Correction Code (ECC)

The Nios® V/m processor core has the option to enable error detection and ECC status reporting for the RAM block, that is the Register file. Each RAM block has its source ID. When an ECC event occurs, the processor transmits the source ID and ECC status to the ECC interface.

  • If the ECC event is a correctable error, the processor continues to operate without correcting the error.
  • If the ECC event is an un-correctable error, the processor halts its current progress and stall. You need to reset either the processor core alone, or the entire system.
Note: To reset the processor core alone, you need to apply the Reset Request Interface to safely reset the Nios® V processor (cleared of any outstanding operations). To reset the entire system, you can use the hard reset interface instead.

The ECC interface allows external logic to monitor ECC errors from the Nios® V/m processor. The interface is a conduit, made up of the following output signals.

  • cpu_ecc_status : Indicates the error status
  • cpu_ecc_source : Indicates the error source.
Table 34.   cpu_ecc_status
2-bits Encoding Description Effects on Software
2’b00 No ECC event None
2’b01 Reserved Not Applicable
2’b10 Correctable single bit ECC error None
2’b11 Un-correctable ECC error Likely fatal and halts the processor.
Table 35.   cpu_ecc_source
4-bits Encoding ECC Source Available
4’b0000 No ECC event Always
4’b0001 General Purpose Register (GPR) Always
4’b0010 ~ 4’b1110 Other RAM Blocks Not Available
4’b1111 Reserved Not Applicable
Note: Due to a limitation with embedded memory blocks, the simulation model of Nios® V processor does not support ECC on Arria® 10 devices.