Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Accessing Tightly Coupled Memory

TCM occupies standard address space like other memory devices connected via system interconnect fabric. The processor configures the address ranges for TCM (if any).

Access from Processor Core

When TCM is present, the Nios® V/g processor core decodes addresses internally to determine if the requested addresses reside in the TCMs. If the address resides in the TCM, the processor core fetches the instruction from instruction TCM or loads the data from the data TCM. The software accesses TCM using regular load and store instructions. From the software’s perspective, there is no difference in accessing a TCM compared to other memory.

Accessing TCM bypasses cache memory. The processor core functions as if the cache were not present for the address span of the TCM. Instructions for managing the cache do not affect the TCM, even if the instruction specifies an address in TCM.

Access from External AXI4-Lite Manager

Any external AXI4-Lite manager can access any TCMs as RAM in the system if it is connected to the TCM’s AXI4-Lite interface. The TCMs support dual-port access, which allows two hosts (processor core and external AXI4-Lite manager) to access the memory simultaneously.

You can access the TCM memories of a Nios® V processor core (Core 1) from another core (Core 2) in a multi-core system. Core 2 acts as the external AXI4-Lite Manager in this setup. Enable this feature by connecting the data bus of Core 2 to the TCM AXI4-Lite subordinate port of Core 1.