Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Data Manager Port

The Nios® V/m processor data bus is implemented as a 32-bit AMBA* 4 AXI-Lite manager port. The data manager port performs two functions:

  • Read data from memory or a peripheral when the processor executes a load instruction.
  • Write data to memory or a peripheral when the processor executes a store instruction.

axsize signal value indicates the load/store instruction size- byte (LB/SB), halfword (LH/SH) or word (LW/SW). Address on axaddr signal is always aligned to size of the transfer. For store instructions, respective writes strobe bits are asserted to indicate bytes being written.

Nios® V/m processor core does not support speculative issue of load/store instruction. Hence, a core can issue only one load or store instruction and waits until the issued instruction is complete.

Table 27.  Data Interface Signals
Interface Signal Role Width Direction
Write Address Channel awaddr Store address [31:0] Output
awprot Unused [2:0] Output
awvalid Store address valid 1 Output

Store address ready

(from memory)

1 Input
Write Data Channel wdata Store data [31:0] Output
wstrb Byte position in word [3:0] Output
wvalid Store data valid 1 Output

Store data ready

(from memory)

1 Input
Write Response Channel bresp

Store response: Non-zero value denotes store access fault


[1:0] Input
bvalid Store response valid 1 Input
bready Constant 1 1 Output
Read Address Channel araddr Load address [31:0] Output
arprot Unused [2:0] Output
arvalid Load address valid 1 Output

Load address ready

(from subordinates)

1 Input
Read Data Channel rdata Load data [31:0] Input

Load response: Non-zero value denotes load access fault


[1:0] Input
rvalid Load data valid 1 Input
rready Constant 1 1 Output