Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

4.1. Processor Performance Benchmarks

Table 61.   Nios® V/g Processor Performance Benchmarks in Intel FPGA Devices for Quartus® Prime Software
Quartus® Prime Edition FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Quartus® Prime Pro Edition Cyclone® 10 224 1864 1.276 1.869
Arria® 10 228 1832
Stratix® 10 265 2067
Agilex™ 7 303 2099
Agilex™ 5 255 2079
Quartus® Prime Standard Edition Cyclone® IV E 81 4316 LE 0.942 1.49
Cyclone® V 117 1886 ALM
Arria® V 121 1917 ALM
Arria® V GZ 211 1859 ALM
Stratix® V 231 1853 ALM
Cyclone® 10 LP 93 4174 LE
Arria® 10 239 1818 ALM
MAX® 10 91 4199 LE
Table 62.  Benchmark Parameters for Quartus® Prime Software
Parameter Settings/Description
Quartus® Prime Pro Edition Quartus® Prime Standard Edition
Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Quartus® Prime Pro Edition software version 24.1. Maximum performance result are based on 10 seed sweep from Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/g processor core (without debug module, internal timer, floating point unit, 4 KB instruction cache, and 4 KB data cache).
  • 128 KB on-chip memory for the instruction and data bus.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 13.2.0
  • CMake Version: 3.27.7
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32im_zicbom -mabi=ilp32
Intel uses the same Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • Superior Performance with Maximum Placement Effort in Quartus® Prime Pro Edition software.
  • High Performance Effort in Quartus® Prime Standard Edition software.
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.