Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents

4.3.4. Floating-Point Unit

The floating-point unit (FPU) implements the single precision floating point instructions. The FPU operates on data stored in thirty-two 32-bits floating-point registers, implemented using M20K memories.

Below are the characteristics of the FPU:

  • Based on RISC-V “F” Standard Extension for Single-Precision Floating-Point
  • Supports floating-point fused multiply-add instructions.
  • IEEE 754-2008 compliant except for:
    • Simplified rounding
    • Subnormal supported on a subset of operations
  • Consumes resource in a typical system as below1:
    • 960 ALMs
    • Five M20Ks memories
    • Five DSP blocks
Note: The Nios® V/g processor adopts the GNU floating point software emulation for double precision floating point operation.
1 System using Arria® 10 FPGA devices.