Nios® V Processor Reference Manual

ID 683632
Date 4/01/2024
Document Table of Contents Address Map

The address map for memories and peripherals in a Nios® V/g processor system is design dependent. The following addresses are part of the processor:
  1. Reset Address
  2. Debug Exception Address
  3. Peripheral Region Base Address
  4. Exception Address
  5. Timer and Software Interrupt Address

You can specify the Reset Address, Debug Exception Address and Peripheral Region Base Address in Platform Designer during system configuration. You can modify the Exception Address stored in the mvtec register. mvtime and mtimecmp register controls the timer interrupt. The msip register bit controls the software interrupt.