Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

8. Strategies for Improving Memory Access Efficiency

Memory access efficiency often dictates the overall performance of your OpenCL™ kernel. When developing your OpenCL code, it is advantageous to minimize the number of global memory accesses. The OpenCL Specification version 1.0 describes four memory types: global, constant, local, and private memories.
Tip: For Intel® oneAPI DPC++/C++ Compiler-specific details, refer to Memory Accesses section in the FPGA Optimization Guide for Intel® oneAPI Toolkits.

An interconnect topology connects shared global, constant, and local memory systems to their underlying memory. Interconnect includes access arbitration to memory ports.

Memory accesses compete for shared memory resources (that is, global, local, and constant memories). If your OpenCL kernel performs a large number of memory accesses, the Intel® FPGA SDK for OpenCL™ Offline Compiler must generate complex arbitration logic to handle the memory access requests. The complex arbitration logic might cause a drop in the maximum operating frequency (fMAX), which degrades kernel performance.

The following sections discuss memory access optimizations in detail. In summary, minimizing global memory accesses is beneficial for the following reasons:

  • Typically, increases in OpenCL kernel performance lead to increases in global memory bandwidth requirements.
  • The maximum global memory bandwidth is much smaller than the maximum local memory bandwidth.
  • The maximum computational bandwidth of the FPGA is much larger than the global memory bandwidth.
    Attention: Use local, private or constant memory whenever possible to increase the memory bandwidth of the kernel.

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