Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents
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5.7.3. Channel Depths

As mentioned in Stalling Channels, channels provide a communication link either between two kernels or between a kernel and an I/O channel. The channel depth counters complement the stall counts in explaining the issues that are causing the channel to stall.

  • If a channel is continuously nearly empty, the read side of the channel is likely working faster than the write side, so the write side must be sped up. The channel depth can probably be reduced.
  • If the channel is full, the write side is likely faster. The channel depth may need to be increased.
  • In more complicated patterns, for example, if the average depth of the channel is far lower than the maximum depth, the write side might be writing a lot of a data in a single attempt and overwhelming the read side but writing slowly the rest of the time. A repetition of this pattern can create bubbles in the pipeline without creating a long stall, so it can be useful to track down using the channel depth counters.
Note: The depth of the channel cannot be directly controlled since the compiler optimizes the channel for better use of area resources and always rounded up based on the requested channel size. So, the final channel depth is approximately 32 bytes, 512 bytes, or a multiple of 1024 bytes.