Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

8.2.3. Optimizing for Two or More Banks of Global Memory

The Intel® FPGA SDK for OpenCL™ Offline Compiler automatically creates a global memory interconnect designed to deliver most of the available global memory bandwidth from the BSP to the kernel system.

The throughput can be saturated using read-only, write-only, or mixed read/write traffic. By default, traffic is interleaved across all available banks. If you find that the throughput is insufficient, Intel® recommends using the -no-interleaving option.