Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

2.4.3. Features of the Schedule Viewer

The Schedule Viewer displays a static view of the scheduled cycle and latency of a clustered group of instructions in your design. Use this report to view loop bottlenecks such as fMAX/II bottlenecks, memory dependency, and occupancy limiter.

In the Schedule Viewer:

  • Columns depict the clock cycles.
  • Rows display a list of kernels, blocks, clusters, and instructions ranked by the order of execution.
  • The red arrows are dependency lines for each block, cluster, or instruction. The arrows show how each block, cluster, or instruction is dependent on other blocks, clusters, or instructions. Hovering over a node (bar) highlights its outgoing dependency lines.
  • Each row represents a node and its start and end cycle.
  • The bars are color-coded. Black indicates a kernel, blue indicates a block, green indicates a cluster, and yellow indicates an instruction.
Figure 23. Schedule Viewer

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