Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

5.5. Temporal Performance Collection

During the run of your host application, the Profiler collects performance counter data at a given sample rate n. After n cycles, the Profiler collects performance counter data and outputs to the profile.mon monitor file.
  • You can control the rate at which the Profiler counters are sampled by setting the Profiler Runtime Wrapper’s -period flag. The specified period is the minimum number of kernel pipeline clock cycles between profiling samples. If you do not set a period, the default behavior is to profile as often as possible.
    Note: For particularly large or long running designs, the amount of data generated by the default temporal period might result in a very large profile.mon and profile.json file. To reduce this file size, either increase the sampling period or turn off temporal profiling.
  • To turn off temporal profiling and instead collect performance data only after a kernel has finished executing, you can set the Profiler Runtime Wrapper’s -no-temporal flag.
  • The Profiler does not automatically collect the profiling information for autorun kernels if you disable temporal profiling, since autorun kernels never finish. You can use the host API call clGetProfileDataDeviceIntelFPGA to obtain profiling data from autorun kernels. For more information about triggering profiling using your host application, refer to Collecting Profile Data During Kernel Execution in the Intel FPGA SDK for OpenCL Pro Edition: Programming Guide.
    Note: If you collect the performance data only at the end of execution, the data is an average representation of the kernel’s overall execution.