Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

2.5. Analyzing Throughput

The <your_kernel_filename>/reports/report.html file contains information that helps you optimize your design based on the throughput knobs.

From the Reports menu's Throughput Analysis drop-down menu, you can analyze throughput Loop Analysis report. The purpose of this view is to show the bottleneck and loop hardware. For each loop, you can identify if it is pipelined and uses hyper-optimized loop structure, and whether user pragma is applied. You can also find out the loop's II and loop speculation value. For more information, refer to Reviewing Loop Information.

Note: Loop Analysis does not report anything about NDRange loops.