Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 12/19/2022
Document Table of Contents

5.9. Intel® FPGA Dynamic Profiler for OpenCL™ Limitations

The Intel® FPGA dynamic profiler for OpenCL™ has some limitations.
  • Profile data is not persistent across OpenCL programs or multiple devices.

    You can request profile data from a single OpenCL program and on a single device only. If your host swaps a new kernel program in and out of the FPGA, the Profiler does not save the profile data.

  • All profiling data is read to the host during execution and is only stored on the device long enough to be read on the next readback. Any reprogram of new designs or restarting the same design results in new profiling data, erasing any previous data that may have existed.

  • Instrumenting the Verilog code with performance counters increases hardware resource utilization (that is, FPGA area usage) and typically decreases performance.

    For information on instrumenting the Verilog code with performance counters, refer to the Instrumenting the Kernel Pipeline with Performance Counters section of the Intel® FPGA SDK for OpenCL™ Programming Guide.