126.96.36.199. Reviewing Block Information
The block view of the System Viewer provides a more granular graph view of the kernel. This view shows the following:
- Fine grained details within kernels (including instructions and dependencies of the instructions) of the generated datapath of computations. The Intel® FPGA SDK for OpenCL™ Offline Compiler encapsulates maximum instructions in clusters for better QoR. The System Viewer shows clusters, instructions outside clusters and their connections.
- Linking from the instruction back to source line by clicking the instruction node.
- Various information about the instructions, such as data width, node’s schedule information in start cycle and latency are provided, if applicable.
The following image is an example of the block view of the System Viewer:
If your design has loops, the Intel® FPGA SDK for OpenCL™ Offline Compiler encapsulates the loop control logic into loop orchestration nodes and the initial condition of the loops into loop input node and their connection to the datapath.
Inside a block, there are often stallable channel RD/WR or memory LD/ST nodes connecting to computation nodes or clusters. You can click different nodes and view the Details pane (or hover over the nodes) to see detailed information about the instruction. For example, you can click the LD/ST nodes to view attributes such as instruction type, width, LSU style, stall-free, global memory, scheduled start cycle, and estimated latency. For stallable nodes, the latency value provided is an estimate. Perform a simulation or hardware run for more accurate latency values.
A cluster has a FIFO in its exit node to store any pipelined data in-flight. You can click the cluster exit node to find the exit FIFO width and depth attribute. The cluster exit FIFO size is also available in the cluster view of the System Viewer. Refer to the following image for cluster exit FIFO details in a block view example.
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