Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization
ID
683506
Date
9/24/2018
Public
1.1. Comparison of the EPE and the Intel® Quartus® Prime Power Analyzer
1.2. Power Estimations and Design Requirements
1.3. Power Analyzer Walkthrough
1.4. Inputs for the Power Analyzer
1.5. Power Analysis in Modular Design Flows
1.6. Power Analyzer Compilation Report
1.7. Scripting Support
1.8. Power Analysis Revision History
1.4.2.1. Waveforms from Supported Simulators
1.4.2.2. .vcd Files from Third-Party Simulation Tools
1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.4.2.4. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.4.2.5. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation
1.5.2. Modular Design Simulation
1.5.3. Multiple Simulations on the Same Entity
1.5.4. Overlapping Simulations
1.5.5. Partial Simulations
1.5.6. Node Name Matching Considerations
1.5.7. Glitch Filtering
1.5.8. Node and Entity Assignments
1.5.9. Default Toggle Rate Assignment
1.5.10. Vectorless Estimation
2.5.1. Clock Power Management
2.5.2. Pipelining and Retiming
2.5.3. Architectural Optimization
2.5.4. I/O Power Guidelines
2.5.5. Memory Optimization (M20K/MLAB)
2.5.6. DDR Memory Controller Settings
2.5.7. DSP Implementation
2.5.8. Reducing High-Speed Tile (HST) Usage
2.5.9. Unused Transceiver Channels
2.5.10. Periphery Power reduction XCVR Settings
2.5.1.1.1. Memory Power Reduction Example
Power usage measurements for a 4K × 36 simple dual-port memory implemented using multiple M4K blocks in a Stratix® device. For each implementation, the M4K blocks are configured with a different memory depth.
M4K Configuration | Number of M4K Blocks | ALUTs |
---|---|---|
4K × 1 (Default setting) | 36 | 0 |
2K × 2 | 36 | 40 |
1K × 4 | 36 | 62 |
512 × 9 | 32 | 143 |
256 × 18 | 32 | 302 |
128 × 36 | 32 | 633 |
Using the MAXIMUM_DEPTH parameter can save power. For all implementations, a user-provided read enable signal is present to indicate when read data is required. Using this power-saving technique can reduce power consumption by as much as 60%.
Figure 17. Power Savings Using the MAXIMUM_DEPTH Parameter
As the memory depth becomes more shallow, memory dynamic power decreases because unaddressed M4K blocks can be shut off using a decoded combination of address bits and the read enable signal. For a 128-deep memory block, power used by the extra LEs starts to outweigh the power gain achieved by using a more shallow memory block depth. The power consumption of the memory blocks and associated LEs depends on the memory configuration.
Note: The SOPC Builder and Platform Designer (Standard) system do not offer specific power savings control for on-chip memory block. There is no read enable, write enable, or clock enable that you can enable in the on-chip RAM megafunction to shut down the RAM block in the SOPC Builder and Platform Designer (Standard) system.