R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.2.2. Resets

Table 47.  Resets
Name Direction Description EP/RP/BP Asynchronous / Synchronous
pin_perst_n Input

This is the reset signal from the board. This pin is not available to the FPGA user logic. If you want to use the PERST# signal in user logic or in the Intel Signal Tap tool, you need to use the pin_perst_n_o signal.

To prevent potential device degradation, the pin_perst_n signal must not be held active if power is supplied to the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express when the FPGA is in user mode. If the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express is planned to be used but not in the early phases of your design cycle, you must configure it in BTI mode using the following qsf assignment:

set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

EP/RP/BP Asynchronous
pin_perst_n_o Output This output signal to the FPGA fabric indicates if PERST# is asserted. EP/RP/BP Asynchronous
ninit_done Input

A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.

You need to instantiate the Reset Release IP and connect the output of that IP to ninit_done.

EP/RP/BP Asynchronous
pX_reset_status_n_o Output

This active-low signal is held low until pin_perst_n has been deasserted and the PCIe Hard IP has come out of reset. This signal is synchronous to coreclkout_hip.

When port bifurcation is used, there is one such signal for each Avalon® Streaming interface. Signals for different interfaces are differentiated by the prefixes p<n>.

Traffic between the user logic in the FPGA core and the IP can start when pX_reset_status_n_o is asserted high.

EP/RP/BP Synchronous to coreclkout_hip.
pX_slow_reset_status_n_o Output This is the equivalent signal for pX_reset_status_n_o in the slow_clk domain. EP/RP/BP Synchronous to slow_clk.
LnX_pipe_direct_reset_status_n (X = 0 - 15) Output This active-low per-lane signal is held low until the PHY RX is out of reset, and when deasserted is an indication to the application logic that the RX data transfer is beginning. PIPE mode Synchronous to pipe_direct_pld_tx_clk_out_o.
LnX_pipe_direct_pld_pcs_rst_n_i (X = 0 - 15) Input User logic deasserts this per-lane signal (driving it to "1") as a part of the reset sequence. Follow the reset sequence as shown in PIPE Direct Reset Sequence. PIPE mode Asynchronous

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