4.5.1. Data Signals
The R-tile Avalon® Streaming Intel FPGA IP for PCI Express* in PIPE direct mode is implemented with a SerDes architecture. The IP has a built-in word serializer for the LnX_pipe_direct_txdata_i[63:0] signals from the user interface and a word deserializer for the LnX_pipe_direct_rxdata_o[63:0] signals to the user interface. For a data rate of 8 GT/s or higher, the IP only exposes 8 bits out of each 10-bit slice for block-encoded data, e.g. bits [7:0] represent byte0, [8:15] represent byte1, [16:31] represent byte 2 etc. Refer to and for the TxData/RxData signal connection guidance.
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