R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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Document Table of Contents

2.1. Overview

R-tile can be configured in one of three primary modes of operation:
  • PCIe Hard IP mode: This mode includes support for (up to Gen5) Endpoint (EP), Root Port (RP) or TLP Bypass (16 lanes maximum). When configured in this mode, R-tile includes a complete protocol stack, including the Transaction, Data Link and Physical Layers.
  • PIPE Direct (protocol controller bypass) for FPGA user custom application needs. In this mode, either one or both of the PCIe and CXL controller stacks are entirely bypassed, and the PIPE SerDes mode interface is exported across the Embedded Multi-die Interconnect Bridge (EMIB) to the FPGA fabric. This mode allows you to implement your own custom controllers in soft IP.
  • Compute Express Link (CXL).
Note: CXL mode is available only to early access customers in the 21.4 release of Intel® Quartus® Prime, but may be widely available in a future release.
Figure 1. R-tile Top-Level Block Diagram

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