R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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3.3.1. Overview

When the TLP Bypass feature is enabled, the R-tile Avalon® -ST IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer.

Note that in TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC. However, you can enable the IP to remove it if the received TLP has the ECRC. The steps on how to do this are described in section ECRC.

The R-tile Avalon® -ST IP in TLP Bypass mode still includes some of the PCIe configuration space registers related to link operation.

R-tile interfaces with the application logic via the Avalon® -ST interface (for the Tx and Rx flow control and all TLP traffic), the Hard IP Reconfiguration interface (for Lite TL’s configuration registers access) and other miscellaneous signals. For details on the usage of the Avalon® -ST interface and the Hard IP Reconfiguration interface, refer to Avalon Streaming Interface and Hard IP Reconfiguration Interface respectively.
Figure 16. R-tile Avalon® -ST IP in TLP Bypass Mode

In TLP bypass mode, R-tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code.

Note: In TLP bypass mode, CvP init and update are not supported.

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