R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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5.2.1. Avalon Parameters

Table 83.   Avalon® Parameters
Parameter Value Default Value Description
Enable Power Management Interface True/False False

When enabled, the Power Management Interface and Hard IP Status Interface are exported. For more details, refer to section Power Management Interface.

Enable Legacy Interrupt True/False False

Enable the support for legacy interrupts. For more details, refer to section Legacy Interrupts.

Enable Completion Timeout Interface True/False False Enable the Completion Timeout Interface. For more details, refer to section Completion Timeout Interface.
Enable Configuration Intercept Interface True/False False Enable the Configuration Intercept Interface. For more details, refer to section Configuration Intercept Interface.
Note: This parameter is only available in EP mode.
Enable PRS Event True/False False Enable the Page Request Service (PRS) Event Interface. For more details, refer to section Page Request Services (PRS) Interface.
Note: This parameter is only available in EP mode.
Enable Error Interface True/False False

Enable the Error Interface. For more details, refer to section Error Interface.

PCIe Header Format True/False False When this parameter is enabled, the header format is the P-tile header format, else it is the Arria 10 header format.
Enable Parity Ports on Avalon® -ST Interface True/False False

When this parameter is enabled, the parity ports appear on the block symbol. These parity ports include: pX_rx_stN_data_par_o, pX_rx_stN_hdr_par_o, pX_rx_stN_prefix_par_o, pX_tx_stN_data_par_i, pX_tx_stN_hdr_par_i, and pX_tx_stN_prefix_par_i ports.

When this parameter is enabled, the application layer must provide valid parity in the Avalon® -ST TX direction.

Power Management State True/False False When this parameter is enabled, PM D3 will enter L3 (pX_sys_aux_pwr_det_i tied to 0). When it is disabled, PM D3 will enter L2 (pX_sys_aux_pwr_det_i tied to 1).

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