R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.5.4. PIPE Direct Reset Sequence

In PIPE Direct mode, your application logic is responsible for managing most of the PHY reset sequence in the FPGA fabric.

Figure 36. PIPE Direct Reset Sequence
Here are the steps shown in the figure above:
  1. PERST# (pin_perst_n) deasserts the IP.
  2. The Soft IP controller deasserts the PIPE per-channel reset (ln0_pipe_direct_pld_pcs_rst_n_i) input to the IP.
  3. The PIPE TX output clock (pipe_direct_pld_tx_clk_out_o) from the IP to the Soft IP controller becomes active.
  4. The fabric sector ready signal (ninit_done) from the FPGA fabric to the IP is asserted.
  5. The PIPE per-channel PHY status signal (ln0_pipe_direct_phystatus_o) from the IP to the Soft IP controller is deasserted.
  6. The PIPE per-channel PHY status signal (ln0_pipe_direct_phystatus_o), PIPE RX status signal (ln0_pipe_direct_rxstatus_o) from the IP to the Soft IP controller are pulsed by the IP indicating RX detection.

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